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Integrated Circuit Systems, Inc.
ICS9214
Rambus XDR Clock Generator
General Description
The ICS9214 clock generator provides the TM necessary clock signals to support the Rambus XDR memory subsystem and Redwood logic interface. The clock source is a reference clock that may or may not be modulated for spread spectrum. The ICS9214 provides 4 differential clock pairs in a space saving 28-pin TSSOP package and provides an off-the-shelf high-performance interface solution. Figure 1 shows the major components of the ICS9214 XDR Clock Generator. These include the a PLL, a Bypass Multiplexer and four differential output buffers. The outputs can be disabled by a logic low on the OE pin. An output is enabled by the combination of the OE pin being high, and 1 in its SMBus Output control register bit. The PLL receives a reference clock, CLK_INT/C and outputs a clock signal at a frequency equal to the input frequency times a multiplier. Table 2 shows the multipliers selectable via the SMBus interface. This clock signal is then fed to the differential output buffers to drive the enabled clocks. Disabled outputs are set to Hi-Z. The Bypass mode routes the input clock, CLK_INT/C, directly to the differential output buffers, bypassing the PLL. Up to four ICS9214 devices can be cascaded on the same SMBus. Table 3 shows the SMBus addressing and control for the four devices.
TM
TM
Features
* * * * * 400 - 500 MHz clock source 4 open-drain differential output drives with short term jitter < 40ps Spread spectrum compatible Reference clock is differential or single-ended, 100 or 133 MHz SMBus programmability for: - frequency multiplier - output enable - operating mode Supports frequency multipliers of: 3, 4, 5, 6, 8, 9/2, 15/2 and 15/4 Support systems where XDR subsystem is asynchronous to other system clocks 2.5V power supply
* * *
Block Diagram
OE OE RegA ODCLK_T0 BYPASS#/PLL
Pin Configuration
AVDD2.5 AGND IREFY AGND CLK_INT CLK_INC VDD2.5 GND SMBCLK SMBDAT OE SMB_A0 SMB_A1 BYPASS#/PLL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD2.5 ODCLK_T0 ODCLK_C0 GND ODCLK_T1 ODCLK_C1 VDD2.5 GND ODCLK_T2 ODCLK_C2 GND ODCLK_T3 ODCLK_C3 VDD2.5
ODCLK_T1 CLK_INT CLK_INC PLL OE RegC ODCLK_T2 ODCLK_C2 SMBCLK OE RegD ODCLK_T3 ODCLK_C3 ODCLK_C1
28-Pin 4.4m m TSSOP
SMBDAT SMB_A0 SMB_A1
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XDR is a trademark of Rambus
ICS9214
Bypass MUX
ODCLK_C0 OE RegB
ICS9214
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
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PIN NAME AVDD2.5 AGND IREFY AGND CLK_INT CLK_INC VDD2.5 GND SMBCLK SMBDAT OE SMB_A0 SMB_A1 BYPASS#/PLL VDD2.5 ODCLK_C3 ODCLK_T3 GND ODCLK_C2 ODCLK_T2 GND VDD2.5 ODCLK_C1 ODCLK_T1 GND ODCLK_C0 ODCLK_T0 VDD2.5
PIN TYPE PWR PWR OUT PWR IN IN PWR PWR IN I/O IN IN IN IN PWR OUT OUT PWR OUT IN IN PWR OUT OUT PWR OUT OUT PWR
DESCRIPTION 2.5V Analog Power pin for Core PLL Analog Ground pin for Core PLL This pin establishes the reference current for the differential clock pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Analog Ground pin for Core PLL "True" reference clock input. "Complementary" reference clock input. Power supply, nominal 2.5V Ground pin. Clock pin of SMBUS circuitry, 5V tolerant Data pin of SMBUS circuitry, 5V tolerant Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs SMBus address bit 0 (LSB) SMBus address bit 1 Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Power supply, nominal 2.5V "Complementary" side of open drain differential clock output. This open drain output needs an external resistor network.. "True" side of open drain differential clock output. This open drain output needs an external resistor network.. Ground pin. "Complementary" side of open drain differential clock output. This open drain output needs an external resistor network.. "True" side of open drain differential clock output. This open drain output needs an external resistor network.. Ground pin. Power supply, nominal 2.5V "Complementary" side of open drain differential clock output. This open drain output needs an external resistor network.. "True" side of open drain differential clock output. This open drain output needs an external resistor network.. Ground pin. "Complementary" side of open drain differential clock output. This open drain output needs an external resistor network.. "True" side of open drain differential clock output. This open drain output needs an external resistor network.. Power supply, nominal 2.5V
2
ICS9214
General SMBus serial interface information for the ICS9214 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D8 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D8 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D9 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host) starT bit T Slave Address D8(H ) WR W Rite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve/Re ce ive r)
Index Block Read Operation
Controlle r (Host) T starT bit Slave Address D8(H ) WR W Rite Beginning Byte = N ACK RT Repeat starT Slave Address D9(H ) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve/Re ce ive r)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
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Not acknowledge stoP bit
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ICS9214
SMB Table: Output Control Register
Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 27,26 24,23 20,19 17,16 Pin # Name Test Mode MULT2 MULT1 MULT0 O DCLK_T/C0 O DCLK_T/C1 O DCLK_T/C2 O DCLK_T/C3 Control Function Reserved for Vendor Multiplier Select Multiplier Select Multiplier Select O utput Control O utput Control O utput Control O utput Control Type RW RW RW RW RW RW RW RW 0 Disable 1 Enable PWD 1 0 0 0 1 1 1 1 1
See Table 2. Disable Disable Disable Disable Enable Enable Enable Enable
Disable = O utput in high-impedance state Enable = O utput is switching
SMB Table: Frequency Multiplier Control Register
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Test Mode Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved for Vendor Type RW RW RW RW RW RW RW RW 0 Disable 1 Enable PWD 0 0 0 0 0 0 0 0
SMB Table: Revision & Vendor ID Register
Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NO TES: 1. PWD = Power Up Default Pin # Name RID4 RID3 RID2 RID1 RID0 VID2 VID1 VID0 Control Function Type R R R R R R R R 0 1 PWD X X X X X 0 0 1
Revision ID
Vendor ID
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ICS9214
PLL Multiplier
Table 2 shows the frequency multipliers in the PLL, selectable by programming the MULT0, MULT1 and MULT2 bits in the SMBus Multiplier Control register. Power up default is 4.
Table 2. PLL Multiplier Selection Byte 0 Bit 6 MULT2 0 0 0 0 1 1 1 1 Bit 5 MULT1 0 0 1 1 0 0 1 1 Bit 4 MULT0 0 1 0 1 0 1 0 1 Frequency Multiplier 3 4 5 6 8 9/2 15/2 15/4 O utput Frequency (MHz) CLK_INT/C = 100 MHz 1 300 3 400 2 500 600 800 450 750 3
CLK_INT/C = 133 MHz 1 400 533 667 800 -3 600 -3 500
NO TES 1 O utput frequencies are based on nominal input frequencies of 100 MHz and 133 MHz. The PLL multipliers are also applicable to spread spectrum modulated input clocks. 2 Default muliplier value at power up 3 O utputs at these settings do not conform to the AC O utput Characteristics, or are not supported. 4 Shaded areas are under development and are not yet supported
Device ID and SMBus Device Address
The device ID (SMB_A(1:0)) is part of the SMBus device address. The least significant bit of the address designates a write or read operation. Table 3 shows the addresses for four ICS9214 devices on the same SMBus.
Table 3. SMBus Device Addresses ICS9214 Device Operation Write 0 Read 1 2 3 Write Read Write Read Write Read Hex Address D8 D9 DA DB DC DD DE DF 11011 1 1 0 1 8-bit SMBus Device Address, Including Oper. SMB_A1 SMB_A0 WR#/RD 0 0 0 1 0 1 0 1 0 1 0 1
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ICS9214
Operating Modes
Table 4: Operating Modes Byte 1 BYPASS#/ OE PLL Bit 7 L H H H H H H H H H H H H H H H H H H X X L H H H H H H H H H H H H H H H H X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 02 Byte 0 ODCLK_T/C3 Z ODCLK_T/C2 ODCLK_T/C1 ODCLK_T/C0 Z Bit 3 X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 12 Bit 2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 12 Bit 1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 12 Bit 0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 12
Z Z Z Z Z Z Z Z CLK_INT/C CLK_INT/C CLK_INT/C CLK_INT/C CLK_INT/C CLK_INT/C CLK_INT/C CLK_INT/C
Z Z Reserved for Vendor Test CLK_INT/C1 Z Z Z Z Z CLK_INT/C Z CLK_INT/C CLK_INT/C Z CLK_INT/C Z CLK_INT/C CLK_INT/C CLK_INT/C CLK_INT/C Z Z Z Z Z CLK_INT/C Z CLK_INT/C CLK_INT/C Z CLK_INT/C Z CLK_INT/C CLK_INT/C CLK_INT/C CLK_INT/C
Z CLK_INT/C Z CLK_INT/C Z CLK_INT/C Z CLK_INT/C Z CLK_INT/C Z CLK_INT/C Z CLK_INT/C Z CLK_INT/C
Notes 1 Bypass Mode 2 Power up default mode
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ICS9214
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Characteristics - Inputs
TA = 0C to +70C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD2.5, AVDD 2.375 2.625 V 125 mA Supply Current I DD2.5, I VDD High-level input VIHCLK 0.6 0.95 V voltage Low-level input VILCLK -0.15 0.15 V voltage CLK_INT, CLK_INC Crossing point VIXCLK 0.2 0.55 V voltage Difference in 0.15 V crossing point VIXCLK voltage Input threshold VTH 0.35 0.5VDD2.5 V voltage High-level input Singled-ended V TH + 0.3 2.625 V voltage for singleV IHSE 1 CLK_IN ended CLK_IN Low-level input -0.15 VTH - 0.3 V voltage for singleV ILSE ended CLK_IN High-level input VIH OE, SMB_A0, 1.4 2.625 V voltage SMB_A1, Low-level input BYPASS#/PLL VIL -0.15 0.8 V voltage High-level input VIHSMB 1.4 3.4652 V SMBCLK, voltage - SMBus SMBDAT Low-level input VILSMB -0.15 0.8 V voltage - SMBus
Notes: 1 When using singled-ended clock input, VTH is supplied to CLK_INTC as shown in Figure 2. Duty cycle of singled-ended CLK_IN is measured at VTH 2 This range of SMBus input high voltages allows the 9214 to co-exist with 3.3V, 2.5V and 1.8V devices on the same SMBus.
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ICS9214
DC Characteristics - Outputs
TA = 0C to +70C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated) SYMBOL MIN TYP MAX PARAMETER CONDITIONS Power within spec to tPU 3 Power up latency outputs within spec SMBus or Mode Select 1 tCO 3 transition to outputs valid State transition latency and within spec Differential output Measured as shown in Fig. VOX 0.9 1.1 crossing voltage 3 Measured as shown in Fig. Output Voltage Swing VCOS 300 350 3. Excludes over and (peak-to-peak singled undershoot. ended) Measured at ODCLK_T/C 0.85 Absolute output low voltage VOLABS pins Reference Voltage for VDD = 2.3V, VOUT = 1V VISET 0.98 1.02 swing control current Ratio of output low IREF is equal to VISET/RRC. IOL/IREF current to reference 6.8 7 7.2 Tolerance of RRC <=+/-1%. current at typical VDD2.5 Measured at ODCLK_T/C Minimum current at IOLABS 45 pins with termination per VOLABS Figure 3. Low-level output voltage IOL = 4 mA VOLSMB 0.4 SMBus Low-level output current VOL= 0.8 V IOLSMB 6 SMBus Tristate output current IOZ Differential clock output pins 50 UNITS ms ms V mV V V -
mA V mA
Notes: 1 There is no output latency or glitches if the value written to an output register is the same as its current value.
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ICS9214
AC Characteristics-Inputs
TA = 0C to +70C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated) PARAMETER CONDITION SYMBOL MIN TYP MAX CLK_INT/CLK_INC cycle time
1
UNITS ns ps % ps ps kHz % % V/ns pF pF ns kHz
tCYCLEIN tcyc-tcyc dtin tR, tF tR-F fINM
3 2
7 over 10,000 cycles 20% to 80% of input voltage 20% to 80% of input voltage 40 175 30 Triangular modulation
11 185 60 700 150 33 0.6 0.54
Cycle-to-Cycle Jitter Input clock duty cycle CLK_INT/CLK_INC rise and fall time Difference between input rise and fall time on same pin of a single device Spread spectrum modulation frequency Spread spectrum modulation index Input clock slew rate Input Capacitance 5 Input Capacitance CLK_INT cycle time SMBus clock frequency
5
mINDEX tsl(I)
3
Non-triangular modulation 20% to 80% of input voltage CLK_INT, CLK_INC VI = VDD2.5 or GND Bypass Mode 1
4 7 10 40 100
CINCLK CIN tCYCLETST fSMB
4 10
Notes: 1 Measured at (VIH(nom) - V IL(nom))/2 and is the absolute value of the worst case deviation. 2 Measured at crossing points for differential clock input or at VTH for singleended clock input. 3 If input modulation is used. Input modulation is not necessary. 4 The amount of allowed spreading for non-triangular modulation is determined by the induced downstream tracking skew. 5 Capacitance measured at f = 1 MHz, DC bias = 0.9V, VAC <100mV.
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ICS9214
AC Characteristics-Outputs
TA = 0C to +70C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated) PARAMETER1 Output clock cycle time Short term jitter (over 1 to 6 clock cycles) Output Phase error when tracking SSC Change in skew Long term average output duty cycle Cycle-to-cycle duty cycle error Output rise and fall times Difference between output rise and fall time on same pin of a single device Dynamic output impedance SYMBOL tCYCLE t J2 tERR,SSC tSKEW DC tDCERR tR, tF f = 400 to 635 MHz f = 635 to 800 MHz 20% to 80% of output voltage 20% to 80% of output voltage, f = 400 to 800 MHz VOL = 0.9 V
3
CONDITION f = 400 to 635 MHz f = 635 to 800 MHz
MIN 1.5 -100
TYP
MAX 2.5 40 30 100 15 55 40 30 300
UNITS ns ps ps ps ps % ps ps ps
TA = 0C to +70C, AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V
45 100
tR-F
-
100
ps
ZOUT4
1000
-
Notes: 1 Max and min output clock cycle times are based on nominal output frequencies of 400 and 667 MHz respectively. For spread spectrum modulated input clocks, the output clocks track the input modulation. 2 Output short-term jitter is the absolute value fo the worst case deviation and is defined in the Jitter section. 3 tSKEW is the timing difference between any two of the four differential clocks and is measured at common mode voltage. 4 Zout is defined at the output pins. 5 Guaranteed by design and characterization, not 100% tested in production
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ICS9214
Clock Output Drivers
Figure 2 shows the clock driver equivalent circuit. The differential driver produces a specified voltage swing on the channel by switching the currents going into ODCLK_T and ODCLK_C. The external resistor RRC at the IREFY pin sets the maximum current. The minimum current is zero. The voltage at the IREFY pin, VIREFY, is by design equal to 1 V nominally, and the driver current is seven times the current flowing through RRC. So, the output low current can be estimated as IOL = 7/ RRC. The driver output characteristics are defined together with the external resistors, R1, R2, and R3. The output clock signals are specified at the measurement points indicated in Figure 2. Table 5 shows example values for the resistors. R1, R2, and R3 and the clock driver output impedance, ZOUT, must match the impedance of the channel, ZCH , to minimize secondary reflections. ZOUT is specified as 1000 Ohms, minimum to accomplish this. The effective impedance can be estimated by: (1000R1/(1000+R1)+R2) R3/(1000R1/(1000+R1)+R2+R3) Pull-up resistor RT terminates the transmission line at the load to minimize clock signal reflection signal reflections. Table 5 shows the resistor values for establishing and effective source termination impedance of 49.2 Ohms to match a 50 Ohm channel. The termination voltages are 2.5 V for VTS and 1.2 V for VT. The resistor values R1 = 38.3 Ohms, R2 = 19.1 Ohms, R3 = 54.9 Ohms and RRC = 200 Ohms can be used to match a 28 Ohm channel.
Table 5. Example Resistor Values and Termination Voltages for a 50 Ohm Channel1 Symbol R1 R2 R3 RT RRC VTS VT Parameter Termination resistor Termination resistor Termination resistor Termination resistor Swing control resistor Source termination voltage Termination voltage Value 39.2 66.5 93.1 49.9 200 2.5 1.2 Tolerance +/- 1% +/- 1% +/- 1% +/- 1% +/- 1% +/-5% +/-5% Unit V V
Notes: 1 A different set of resistors is used in Figure 2 when testing for maximum output current of the clock driver (IOLABS). These resistors are: R1 = 34, R2 = 31.8, R3 = 48.7, RT=28, RRC = 147
Supply Voltage
CLK_INC CLK_INT
VTH
Input
CLK_INT
Input
XDR Clock Generator a. Differential input
XDR Clock Generator b. Single-ended input
Figure 1. Differential and single-ended reference clock inputs
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ICS9214
Input Clock Signal
The ICS9214 receives either a differential or single-ended reference clock (CLK_INT/C). When the reference input clock is from a differential clock source, it must meet the voltage levels and timing requirements listed in the DC Characteristics - Inputs and AC Characteristics - Inputs tables. For a singled-ended clock input, an external voltage divider and a supply voltage, as shown in Figure 2, provide a reference voltage VTH at the CLK_INC pin to determine the proper switching point for CLK_INT. The range of VTH is specified in the DC Characteristics - Inputs table.
VTS
ODCLK_T
R1 R2 R3
Measurement Point ZCH
VT RT
Swing Current Control
ISET
Differential Driver VTS
ODCLK_C
Measurement Point ZCH
R1 R2 R3
VT RT
RRC
Figure 2. Example System Clock Driver Equivalent Circuit
VH 80% V(t) 20% VL tF tR
Figure 3. Input and Output Voltage Waveforms
ODCLK_T
Vx+ Vx,nom Vx-
ODCLK_C
Figure 4. Crossing-point Voltage
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ICS9214
Power Sequencing
Supply voltages for the ICS9214 must be applied before, or at the same time and external input and output signals.
ODCLK_T
ODCLK_C
tCYCLE,i
tCYCLE,i+1
tJ = tCYCLE,i - tCYCLE, i+1 over 10,000 consecutive cycles
Figure 5. Cycle-to-cycle Jitter
ODCLK_T ODCLK_C
t4CYCLE, i
t4CYCLE, i+1
tJ = t4CYCLE, i - t4CYCLE, i+1 over 10,000 consecutive cycles
Figure 6. Short-term Jitter
ODCLK_T
Cycle (i)
Cycle (i+1)
ODCLK_C
tPW- (i) tCYCLE (i)
tPW+ (i)
tPW- (i+1) tCYCLE (i+1)
tPW+ (i+1)
tDC,ERR = tPW+(i) - tPW+(i+1) and tPW-(i) - tPW-(i+1)
Figure 7. Cycle-to-cycle Duty Cycle Error
fNOM
(1-PM,IN)*fNOM 0.5/fM,IN t 1/fM,IN
Figure 8. Input frequency Modulation
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ICS9214
Phase Noise
The 9214 meets the single side band phase noise spectral purity for offset frequencies between 1 MHz and 100 MHz as described by the equation: 10log[1+(50 x 106/f)2.4] -138 dBc/Hz This equation is shown in Figure 9. Phase Noise Plot
SSB Spectral Purity L(f), dBc/Hz
-100 -110 -120 -130 -140 -150
10 log[1 + ( 50x 10 6 / f )2. 4 ] -138
( U p p e r L im it )
10
6
10 10 Offs e t Fre q u e n cy f , H z
7
8
10
9
Figure 9 : Phase Noise Plot
Sample points are for this equation are shown in Table 6. Phase Noise Data Points
Offset Frequency (MHz)
1
5
10
15
20
40
80
100
SSB Spectral -97 -114 -121 -125.2 -128 -133.7 -136.8 -137.3 Purity (dBc/Hz)
Table 6 : Phase Noise Data Points
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ICS9214
4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil)
N
c
(25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
SYMBOL
L
INDEX AREA
E1
E
12 D
A A1 A2 b c D E E1 e L N a aaa VARIATIONS N
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
A2 A1
A
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
-Ce
b SEATING PLANE
28
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
10-0035
Ordering Information
ICS9214yG LF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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ICS9214
Revision History
Rev. 0.1 Issue Date Description Updated SMBus table Byte 2, Bit 3 from:0 to:1. 3/30/2005 Updated PLL Multiplier Selection Table, from: Byte 1 to: Byte 0, and Bit 2,1,0, to: Bit 6,5,4. Updated Ordering Information from "Lead Free" to "Annealed Lead Free" Added Phase noise spec Removed unsupported speeds from PLL Multiplier Selection, Changed minimum output raise, fall times from 140ps to 100 ps 4/6/2005 Compliant with Rev 0.81 of XCG spec. 1. Changed write address from D2 to a valid address (D8) 4/22/2005 2. Changed read address from D3 to a valid address (D9) Page # 4-5,15
A B
Various 3
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